September 12-15, 2017
In recent years, traditional processors have not been able to directly translate chip fabrication technology advances intro performance gains. To keep satisfying the demand for computing power, there is a shift from homogeneous machines to heterogeneous architectures combining different kinds of processors (CPUs, GPUs, DSPs, FPGAs, and other accelerators). While this approach has allowed significant performance and energy efficiency benefits, heterogeneous systems are often highly difficult to program with existing tools. To reduce the cost of system development, reengineering techniques emerge as a solution which may help to balance ease-of-development with better performance, better reliability, and lower maintenance costs.
The RePara2017 workshop it aims to join experts from related disciplines to share recent advances in different areas contributing to better transformation of new and legacy applications to different programming models for diverse computing devices in the context of parallel heterogeneous architectures.
Scope and Interests
Topics of interest include, but are not limited to:
- High-level parallel programming models, libraries and languages for Heterogeneous Parallel Platforms.
- Compiler support for Heterogeneous Parallel Systems.
- Description languages for Heterogeneous Parallel Platforms.
- Parallel patterns for Heterogeneous Platforms.
- Autonomic management of Power/Performance trade-offs.
- Automated kernel identification and assessment.
- Software refactoring approaches for parallel programming models.
- Transformations from source code to reconfigurable hardware.
- Integration of FPGA accelerators into refactored software.
- Runtimes for software coordination and task mapping in Heterogeneous Parallel Platforms.
- Scheduling for Heterogeneous Parallel Platforms.
- Performance modeling and prediction in Heterogeneous Parallel Platforms.
- Energy efficiency monitoring and prediction in Heterogeneous Parallel Platforms.
- Software quality assessment in parallel programming models with special attention to maintainability.
- Applying partitioning and mapping for parallel Heterogeneous computing architectures.
- Application experiences of refactoring to software in industrial domains.
Accepted paper will be published in the proceedings of the ParCo 2017 Conference.
Extended version of selected papers from the workshop will be invited by the RePara2017 program committee for publication, after further revision, in an special issue of Journal of Supercomputing (Springer, ISSN: 0920-8542, Impact Factor 2014: 0.858).
Please email inquiries concerning the workshop to J. Daniel Garcia.