Application partitioning and mapping techniques for heterogeneous parallel platforms

13 March, 2017

In recent years, performance gains provided by clock and ILP techniques have considerably slowed down. As a result, parallel programming has become the dominant programming paradigm used to improve performance in multi-core devices. In line with this, parallel use of specialized accelerators has started gaining importance.
However, adapting legacy source code in order to make use of these technologies is a time consuming and error prone task, requiring specialised knowledge.
The main goal of this Thesis is to simplify the task of transforming sequential legacy code into parallel code. This code will be capable of making full use of the different computing devices that an heterogeneous parallel platform can have, such as modern CPUs, GPUs, FPGAs, and DSPs. With this, it is possible to improve sequential code based on different criteria, such as time performance.
As a result, we propose an architecture description language to describe heterogeneous parallel platforms. We suggest a new software annotation syntax to describe the behaviour of the code from a high-level point of view while preserving its maintainability, along with automatic annotation techniques. Finally, we propose a set of task partitioning techniques to split the code and execute it in parallel using the available computing devices. Results aim to demonstrate that the proposed techniques can be applied to different accelerator devices and source code, and that the chosen metrics are improved with respect to the original sequential code.

title={Application partitioning and mapping techniques for heterogeneous parallel platforms},
author={Sotomayor Fern{\’a}ndez, Rafael},